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Computer history TNO-FEL:
CDC CYBER 930-11

CDC CYBER 930-x1 (photo: Control Data CDC 930 leaflet)
Control Data CYBER 930-11/ -31
(photo from CDC's CYBER 930 leaflet)

This air cooled, office series of systems was built in Control Data's Canadian factory. It was the first system that did not have the 6000-series (or -170) compatibility mode. It only ran virtual mode or 180-state for NOS/VE. Although targeted at the mini-market, the system was never sold as a mass-market computer.

The CYBER 930 offered two levels of performance via two models: the 930-11 and 930-31 which were compatible with the entire CYBER 180 series of systems. As entry-level members of the CYBER 180 family of general-purpose processors, the models 930-11 and -31 (later 932-11 and -31) featured CMOS technology to provide high reliability, compact packaging, low power consumption and high-speed computation.

Central Processor Features

The CYBER 930 models featured a micro-coded central processor that could execute the CYBER 180 virtual address and instruction repertoire of the NOS/VE operating system. The CPU was a high-speed arithmetic unit composed of five autonomous functional processing units, which support business data processing instructions, address calculation, integer, boolean, shift and floating point operations. It operated independently from the input/output processors, which did all input and output (I/O), and is therefore free to carry on computation unencumbered by the I/O requirements of the system. The CPU featured a comprehensive, multilevel interrupt facility, extensive built-in security features, and a powerful instruction retry facility. The instruction issue unit contained two three-word pipelines, which supported historical branch prediction and simultaneous execution of several instructions.

Central Memory Features

The central memory consisted of four logically independent banks composed of 256K bit metal-oxide semiconductor (MOS) circuits, which provided a complete read/write cycle time of 400 nanoseconds (major cycle) for one bank. The banks were phased so that successive addresses were in different banks, enabling memory to operate at much higher rates than the basic bank cycle time.

Central memory access to/from the CPU and/or each of the 1/0 clusters was provided via a bus arbitrator, which manages the system's multibus memory design. This memory design allowed replacement of up to two failing bits without performance degradation, as well as Single-Error Correction/Double-Error Detection (SECDED) logic. When a word was read from memory, all single-bit errors were corrected. Multiple-bit errors were detected and reported to the system via the system's maintenance access channel and the maintenance control unit. The CYBER 930 at TNO as configured with 32 MB.

Input/Output features

The system featured one I/O cluster that consists of five I/O processors and six data channels, which operate independently and simultaneously as stored-program computers (the old CDC PP-concept). An additional I/O cluster enabled the site to expand the system to a total of ten I/O processors and 12 data channels.

Simultaneous data transfer rate to and from 1/0 processor memory was 8 MBps (max.). The date rate directly to/from central processor memory was 20 MBps. All channels were bi-directional and independent.

The I/O cluster also supported remote system management and maintenance via a selected I/O processor. The console monitored the operation of the system, performed system integrity verification through diagnostics, detected system faults, and took corrective action.

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