Core Memory

6000 series memory block (4096 words,12bits) In early days (CDC 6000-series) the memory had no parity and was build up from core memory blocks (6.75 by 6.75 by 3.625 inches tall), each containing 4096 lines of 12 bits. Five blocks in a row comprised central memory. One block occupied the memory of a single Peripheral Processor or PP.
Note: the background of these pages is derived from a macro photograph of a core memory layer.

CDC 6000 series and CYBER 70-series core memory.
One of the 12 layers of a memory block showing 64*64 bits.
(can be enlarged to real size)

Macro photo of one of the core planes.

Core memory in action

Source: [Thornton70]

Core memory relies upon the magnetic hysteresis loop. A certain electro-magnetic threshold field (or current through a wire) is required to change the setting of the direction of magnetization in a toroidally shaped core. The current can also be the sum of the current flows through two orthogonal wires passing through the core.

Depending on the direction of the current in these two wires, a positive or a negative field will appear at the core. It can be seen that a "halfcurrent" will produce a "half-field" which can be held just below the KNEE of the magnetic hysteresis loop (also called B-H curve).
This knee-point is the point beyond where the magnetic direction might change under influence of a stronger magnetic field. Thus two positive half-currents will produce a full-field which will be substantially above the coercivity of the core magnetic material resulting in a remanent magnetization following removal of the full-field.

It should be clear that two orthogonal wires can be made to select one core from a two-dimensional array. In such a case only one core at the coincidence of the X line and the Y line will experience a full field. All other cores on the X and Y lines will experience a half-field, while the rest of the cores will remain unaffected by any field.

During a full-field condition the magnetic core will switch states, taking a finite time interval to accomplish the switch. This time interval is 400 nanoseconds in the storage module for the CDC 6600 computer and is a function of the composition of the ferrite and the dimensions of the core.

Multiple planes

I-wires blocking 11 out iof 12 bit planes

A two-dimensional array of cores is shown in the figure at the right. The two orthogonal wires X and Y can be seen along with three other wires passing through each core. A diagonal wire is a convenient means for sensing the voltage induced during a core switching operation and is labeled the SENSE, or S wire. The other orthogonal wires are included as a convenient means for counteracting the fields induced by the X and Y lines. These are labeled INHIBIT, or I wires, and effectively allow the array to grow from two dimensions to three.

The CDC 6000 series used separate inhibit lines for each bit or layer in the third dimension, while the X and Y lines thread through the whole array. Each "plane" is a two-dimensional array of 4096 bits. There is a total of twelve planes in a module, making up the twelve bits of word length. Bit control is accomplished through the X inhibit and Y inhibit wires on each plane.

Read and (re)write

A typical readout is accomplished by pulsing the X and Y lines with half currents in a direction such as to produce a "positive" full-field in each of the twelve cores corresponding to the selected address. One can easily predict the switching behavior of a core at a selected address for the two cases of interest. With a "1" previously stored in the core, a negative remanent state exists before the readout. The full readout field causes the core to follow the hysteresis curve, finally coming to rest in "opposite state". The total magnetic flux change is detected on the SENSE winding as a "1". If this signal is sampled and stored, the WRITE cycle of the storage unit can be used to replace the "1" in the core. A WRITE cycle follows the READ cycle by causing a "negative" full field at the selected address causing the restore of the "1" state.

The second case of interest is found with the initial magnetic remanent state represents a stored "zero." The positive full-field during the READ cycle causes very little actual flux change, resulting in a very small signal. During the following WRITE cycle, the INHIBIT windings are energized by a positive half-field counteracting the effect of the full negative X-Y drive.

The type of storage just described is known as "destructive readout" or DRO storage because a single READ requires a following RESTORE to retain the data.

[Thornton70] "Design of a computer: The Control Data 6600" (title in 6000 console display lettering!), J.E.Thornton; Scott, Foresman and Company, 1970; Library of Congres Catalog No. 74-96462

(with special thanks to Mark Riordan who provided the initial basis for this page)

MuseumWaalsdorp@tno.nl