Museum Waalsdorp: SC//MP microcomputer

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Input/Output signals of the "SC//MP"processor

Description

Mnemonic Functional Name Description

NRST Reset Input Set high for normal operation. When set low, aborts in-process operations. When returned high, internal control circuit zeroes all programmer-accessible registers; then, first instruction is fetched from memory location 000116

CONT Continue Input When set high, enables normal execution of program stored in external memory. When set low, SC/MP operation is suspended (after completion of current instruction) without loss of internal status

NBREQ Bus Request In/Output Associated with SC/MP internal allocation logic for system bus. Can be used as bus request output or bus busy input. Requires external load resistor to Vcc

NENIN Enable Input Associated with SC/MP internal location logic for system bus. When set low, SC/MP is granted access to system busses. When set high, places system busses in high-impedance (TRI-STATE(r)) mode.

NENOUT Enable Output Associated with SC/MP internal allocation logic for system bus. Set low when NENIN is low and SC/MP is not using system busses (NBREQ-high. Set high at all other times.)

NADS Address Strobe Output Active-low strobe. While low, indicates that valid address and status output are present on system busses.

NRDS Read Strobe Output Active-low strobe. On trailing edge, data are input to SC/MP from 8-bit bi-directional data bus. High-impedance (TRI-STATE(r)) output when input/output cycle is not in progress.

NWDS Write Strobe Output Active-low strobe. While low, indicates that valid output data are present on 8-bit bi-directional data bus. High-impedance (TRI-STATE(r)) output when input/output cycle is not in progress.

NHOLD Input/Output Cycle Extend Input When set low prior to trailing edge of NRDS or NWDS strobe, stretches strobe to extend input/output cycle; that is, strobe is held low until NHOLD signal is returned high.

SENSE A Sense/interrupt Request Input Serves as interrupt request input when SC/MP internal IE (interrupt Enable) flag is set. When IE flag is reset, serves as user-designated sense condition input. Sense condition testing is effected by copying status register to accumulator.

SENSE B Sense Input User-designated sense-condition input. Sense-condition testing is effected by copying status register to accumulator.

SIN Serial Input to E register Under software control, data on this line are right-shifted into E register by execution of SIO instruction.

SOUT Serial Output from E register Under software control, data are right-shifted onto this line from E register by execution of SIO instruction. Each data bit remains latched until execution of next SIO instruction.

FLAGS 0,1,2 Flags Outputs User-designated general-purpose flag outputs of status register. Under program control, flags can be set and reset by copying accumulator to status register.

AD00-AD11 Address bits 00 through 11 Twelve (TRI-STATE(r)) address output lines. SC/MP outputs 12 least significant address bits on this bus when NADS strobe is low. Address bits are then held valid until trailing edge of read (NRDS) or write (NWDS) strobes. After trailing edge of NRDS or NWDS strobe, bus is set to high (TRI-STATE(r)) mode until next NADS strobe.

Output at NADS Time

Mnemonic	Functional Name	Description
DB0	Address Bit 12	Fourth most significant bit of 16-bit address
DB0	Address Bit 13	Third most significant bit of 16-bit address
DB2	Address Bit 14	Second most significant bit of 16-bit address
DB3	Address Bit 15	Most significant bit of 16-bit address
DB4	R-Flag	When high, data input cycle is starting; when low, data output cycle is starting
DB5	I-Flag	When high, first byte of instruction is being fetched
DB6	D-Flag	When high, indicates delay cycle id started; that is, second byte of DLY instructions being fetched
DB6	H-Flag	When high, indicates that HALT instruction has been executed. (In some system configurations, the H-Flag output is latched and, in conjunction with the CONTinue input, provides a programmed halt).

Scheme of the SC//MP processor
(full size 70 KB)

MuseumWaalsdorp@tno.nl

Mnemonic	Functional Name	Description
NRST	Reset Input	Set high for normal operation. When set low, aborts in-process operations. When returned high, internal control circuit zeroes all programmer-accessible registers; then, first instruction is fetched from memory location 000116
CONT	Continue Input	When set high, enables normal execution of program stored in external memory. When set low, SC/MP operation is suspended (after completion of current instruction) without loss of internal status
NBREQ	Bus Request In/Output	Associated with SC/MP internal allocation logic for system bus. Can be used as bus request output or bus busy input. Requires external load resistor to Vcc
NENIN	Enable Input	Associated with SC/MP internal location logic for system bus. When set low, SC/MP is granted access to system busses. When set high, places system busses in high-impedance (TRI-STATE(r)) mode.
NENOUT	Enable Output	Associated with SC/MP internal allocation logic for system bus. Set low when NENIN is low and SC/MP is not using system busses (NBREQ-high. Set high at all other times.)
NADS	Address Strobe Output	Active-low strobe. While low, indicates that valid address and status output are present on system busses.
NRDS	Read Strobe Output	Active-low strobe. On trailing edge, data are input to SC/MP from 8-bit bi-directional data bus. High-impedance (TRI-STATE(r)) output when input/output cycle is not in progress.
NWDS	Write Strobe Output	Active-low strobe. While low, indicates that valid output data are present on 8-bit bi-directional data bus. High-impedance (TRI-STATE(r)) output when input/output cycle is not in progress.
NHOLD	Input/Output Cycle Extend Input	When set low prior to trailing edge of NRDS or NWDS strobe, stretches strobe to extend input/output cycle; that is, strobe is held low until NHOLD signal is returned high.
SENSE A	Sense/interrupt Request Input	Serves as interrupt request input when SC/MP internal IE (interrupt Enable) flag is set. When IE flag is reset, serves as user-designated sense condition input. Sense condition testing is effected by copying status register to accumulator.
SENSE B	Sense Input	User-designated sense-condition input. Sense-condition testing is effected by copying status register to accumulator.
SIN	Serial Input to E register	Under software control, data on this line are right-shifted into E register by execution of SIO instruction.
SOUT	Serial Output from E register	Under software control, data are right-shifted onto this line from E register by execution of SIO instruction. Each data bit remains latched until execution of next SIO instruction.
FLAGS 0,1,2	Flags Outputs	User-designated general-purpose flag outputs of status register. Under program control, flags can be set and reset by copying accumulator to status register.
AD00-AD11	Address bits 00 through 11	Twelve (TRI-STATE(r)) address output lines. SC/MP outputs 12 least significant address bits on this bus when NADS strobe is low. Address bits are then held valid until trailing edge of read (NRDS) or write (NWDS) strobes. After trailing edge of NRDS or NWDS strobe, bus is set to high (TRI-STATE(r)) mode until next NADS strobe.