CDC CYBER 180 series of systems at TNO
CDC CYBER 180-835
The CDC Cyber 180-835 had a sixty-bit word size, 524,288 words of semiconductor storage with error correction code. Ten (fifteen or twenty) peripheral processors (PPs), each with 4096 12-bit (plus one parity bit) words of storage. The processor included 2048 words of cache memory, floating point hardware, eight addressing, eight operand and eight increment registers. Central processor interrupts through an exchange jump. Twelve (or 24) 12-bit (plus one parity bit) data channels. Includes system console and required cooling equipment; chilled water required. Included a 18001-1 data channel converter (conversion 170 channel to 3000 channel).
Initially called CYBER 170-835, the same system was marketed as CYBER 180-835 after the announcement of the NOS/VE virtual memory operating system. The 835 systems were often used in dual-state, meaning that both a 170-instruction and a 180-instruction state were in use simultaneously. In operating system terms: the 170-state was used by NOS or NOS/BE and the 180-state by the NOS/VE operating system. This allowed a (nearly) seamless transition from the (old) static memory operating system to the virtual memory operating system.
CDC CYBER 180-840A
As part of the CYBER 180 family, this (at that time) high-performance system used a combination of subnanosecond emitter-coupled logic (ECL) circuits and large scale integration (LSI) arrays to provide high-reliability compact packaging, low power requirements, and high computation speeds. The Model 840A had a micro-coded single central processor that included cache memory and was capable of supporting up to l6M 64-bit words of main memory (134 Mbytes).
The central processor was a high-speed arithmetic unit, communicating only with central memory. It operated independently from the peripheral processors, which did all input/output, and is free to carry on computation unencumbered by the input/output requirements.
Instruction and program address pipelines held instructions and addresses during execution, allowing several instructions to be in different stages of execution simultaneously.
The Model 840A central memory was composed of eight logically independent banks that are composed of 256K metallic-oxide semiconductor (MOS) chips. The MOS chips provided a complete read/write cycle time for one bank of 384 nanoseconds (major cycle). The banks were phased so that successive addresses are in different banks to permit operation of central memory at much higher rates than the basic bank cycle time.
Three central memory interface ports are provided by the Model 840:
- Central processor/port
- Input/output unit/port
- External port for Control Data MAP or CYBERPLUS processors
A data distributor provided service to each of the memory interface ports on a priority basis and distributed data between the ports and the memory. The data distributor also contained the Error Correction Code (ECC) generators and the Single Error Correction/Double-Error Detection (SECDED) logic. When a word was read from memory, any single-bit-errors were corrected. Multiple-bit errors were detected and reported to the system via the maintenance access channel and the maintenance control unit.
Input/Output Unit (IOU)
The IOU consisted of ten peripheral processors (PP) and 12 data channels that operated independently and simultaneously as stored-program computers. Options could be selected to expand to 15 or 20 peripheral processors overall, plus adding an additional 12 data channels. Each channel could transfer data into or out of the system at a maximum rate of 250 nanoseconds per 12-bit word. All channels were bidirectional, transferring 12 bits (plus parity), and each could be connected to one or more external devices. Channels could be operated simultaneously. The IOU also contained a maintenance control unit (MCU) that was a selected peripheral processor programmed to initialize the system. It monitored the operation of the system, performed system integrity verification through diagnostics, detected system faults, and took corrective action.
The system included a reserved communications line interface for use in providing remote technical assistance (RTA). Remote maintenance or RTA could be performed by technical specialists dialling into this special interface.
The Model 840 was capable of dual state operation, where the central processor executes two different instruction sets. The first set, called the 170-state, executed the instruction set required by the NOS or NOS/BE operating system, its products, utilities, and applications. The 170-state supported real memory addressing, uses 60-bit words (6-bit characters) and a 12-bit mode for the peripheral processors.
The second set, called the 180-state, executed the instruction set required by the NOS/VE operating system, its products, utilities and applications. The 180-state supports virtual memory addressing, used 64-bit words (8-bit bytes) and a 16-bit mode for the peripheral processors.
The central processor could change states dynamically, running both the NOS(/BE) and NOS/VE operating systems simultaneously. Central memory was divided between the two states at system initialization time. The IOU (input-output unit) was also divided at system initialization time so that peripheral processors were assigned to a state.
For the 170-state, the peripheral processors used a 12-bit word mode; in the 180-state, the peripheral processors used a 16-bit word mode.
CDC CYBER 930-11
This air-cooled, office series of Cyber systems was built in Control Data’s Canadian factory. It was the first system that did not have the 6000-series (or -170) compatibility mode. It only ran virtual mode or 180-state for NOS/VE. Although targeted at the mini-market, the system was never sold as a mass-market computer.
The CYBER 930 offered two levels of performance via two models: the 930-11 and 930-31 which were compatible with the entire CYBER 180 series of systems. As entry-level members of the CYBER 180 family of general-purpose processors, the models 930-11 and -31 (later 932-11 and -31) featured CMOS technology to provide high reliability, compact packaging, low power consumption and high-speed computation.
Central Processor Features
The CYBER 930 models featured a micro-coded central processor that could execute the CYBER 180 virtual address and instruction repertoire of the NOS/VE operating system. The CPU was a high-speed arithmetic unit composed of five autonomous functional processing units, which support business data processing instructions, address calculation, integer, Boolean, shift and floating point operations. It operated independently from the input/output processors, which did all input and output (I/O), and was, therefore, free to carry on computation unencumbered by the I/O requirements of the system. The CPU featured a comprehensive, multilevel interrupt facility, extensive built-in security features, and a powerful instruction retry facility. The instruction issue unit contained two three-word pipelines, which supported historical branch prediction and simultaneous execution of several instructions.
Central Memory Features
The central memory consisted of four logically independent banks composed of 256K bit metal-oxide semiconductor (MOS) circuits, which provided a complete read/write cycle time of 400 nanoseconds (major cycle) for one bank. The banks were phased so that successive addresses were in different banks, enabling memory to operate at much higher rates than the basic bank cycle time.
Central memory access to/from the CPU and/or each of the 1/0 clusters was provided via a bus arbitrator, which manages the system’s multibus memory design. This memory design allowed replacement of up to two failing bits without performance degradation, as well as Single-Error Correction/Double-Error Detection (SECDED) logic. When a word was read from memory, all single-bit errors were corrected. Multiple-bit errors were detected and reported to the system via the system’s maintenance access channel and the maintenance control unit. The CYBER 930 at TNO as configured with 32 MB.
The system featured one I/O cluster that consisted of five I/O processors and six data channels, which operated independently and simultaneously as stored-program computers (the old CDC Peripheral Processor-concept). An additional I/O cluster enabled the site to expand the system to a total of ten I/O processors and 12 data channels.
Simultaneous data transfer rate to and from 1/0 processor memory was 8 MBps (max.). The date rate directly to/from central processor memory was 20 MBps. All channels were bi-directional and independent.
The I/O cluster also supported remote system management and maintenance via a selected I/O processor. The console monitored the operation of the system, performed system integrity verification through diagnostics, detected system faults, and took corrective action.