Computer history: Micro Electronic Computer (1970)

 

Micro Electronic Computer (MIER) – 1966

 
The Micro Electronic Computer, called ‘MIER’ (Dutch for ant), was developed and built by TNO in 1966. At that time, the use of microelectronics was still in its infancy. As TNO lacked funds for buying equipment and the amount of manpower was not an issue, the MIER was developed and built by the digital technologies department by four persons. The design of the MIER was based on previous experiences at the TNO Physics Laboratory that were gained by applying digital techniques in developing calculation circuits.

The MIER was equipped with the first integrated circuits manufactured by Texas Instruments. These integrated circuits had a flat package design, where specific techniques were used for assembly. The core memory module with 4096 × 20 bits was purchased separately. The electronic control for the memory module (read-write circuits) was developed in-house at the laboratory.

The ICs of the first prototype were clamped in special sockets. Together with the hand-applied wiring, this led to cards with gigantic dimensions. The prototype of the MIER was therefore named MAMMOET.

The program input for the MIER was either entered manually using the switches on the control panel or by reading a papertape with the connected papertape reader.

The MIER was a computer developed for real-time process control. The computer had a very limited set of instructions, but sufficient enough for the real-time control that was envisioned. With the knowledge of today, the acronym ‘MIER’ could better stand for ‘Minimal Instruction set Electronic unit for Real-time process control‘ (according to the system designer in 2019).

From March 1971, the MIER was used to control the ‘Computer Assisted Inertialess Scanning System Array’ (CAISSA radar). End of December 1975, it was concluded that the MIER showed too many malfunctions to be a reliable system for the radar. A replacement was considered which was acquired in 1977, an Alpha-LSI.

Global design and operation of the MIER

Information is retrieved from the core memory M (Memory) via Read Amplifiers (RA) and is written into the Memory Register (MR). Information to be stored is first placed into the MR and then written into the core memory via Write Amplifiers (WA). The MR has the function of a buffer register.
Immediately after reading information from the memory into the MR, the MR contents are (re)written towards the same memory location. However, depending on the type of processor instruction, the content of the MR to be written could be modified. The read and (re)write of the memory location is performed in a single memory cycle.

The Memory Address Register (MAR) determines the address of the memory location being read. The MAR, therefore, controls decoding matrices to electronically address the right memory location. The MAR is 13 bits wide. In principle, 8192 (2¹³) memory addresses can be selected with this design. The MIER, however, is equipped with 4,096 words of memory that are addressed by the last 12 address bits.

The memory word size for instructions and data is 20 bits. The least significant bit (LSB) of a word is the parity bit. The parity bit is generated when writing data (19 bits). If the number of bits with a value of 1 is an even number, the parity (bit) is set to one. If the number of bits with the value 1 is odd, the parity (bit) becomes zero. After reading a word from the memory to the MR, a PArity Check (PAC) circuit checks whether the total number of bits with a value of 1 in the 20-bit word is odd. If not, a read error occurs. Further processing stops with an illuminated “parity fault” indication on the control panel.

If the word read is an instruction, it is placed in the Memory Register (MR). The address part of the word is copied to the Data Address Register (DAR) and the instruction part to the Instruction Register (IR). The two registers together with the Modification Register (MOR), Program Address Register (PAR), Memory Address Register (MAR) and the AU2 circuit (Adding Unit 2) form the control part of the MIER.
If the word read is not an instruction, it is copied to one of the data registers Accumulator (AC), Multiplier / Quotient (MQ), Input / Output Address register (ILO), Input / Output Data register (IAD) and the circuit AU1 (Adding Unit 1). This value can also be copied to one of the Flip-Flops (FF) or the Modification Register (MR).

Each instruction has a switching and calculation period of ten switching times of 0.5 µsec (minor clock cycle). Incidentally, more than ten switching times are required when processing the multiplication, division, and shift instructions.
A memory word cannot tell whether it contains an instruction or a data word. The system assumes that there are always instructions on the subsequent addresses the program cycles through.
The address of another word can be specified in an instruction. For example, an action could be performed with the content of such a word.

An instruction word has a 13-bit address part (bits 1 to 13) and a 6-bit instruction part (bits 14 to 19) which is copied to the Instruction Register (IR). The address part is copied to the Data Address Register (DAR). To execute an instruction in a meaningful way, a second memory cycle will be performed during the switching period of the computer in which the information to be processed is read from memory. Only after that, the calculation period can start.
in a data word, bit 1 indicates the sign: 0 = positive, 1 = negative. The absolute value is found in bits 2 through 19.

The computer cycle works as follows:

1. Generate the address for the next instruction
2. Put the address into the MAR
3. Read the memory at the address the MAR points to
4. Copy the instruction part in the MAR into the Memory Register (MR)
5. Copy the instruction part from the MR into the Instruction Register (IR)
6. Copy the address part from the MR into the Data Address Register (DAR)
7. Copy the instruction part from the MR into the memory address the MAR points to (rewrite)
8. Copy the address from the DAR to the MAR
9. Read data from the memory location pointed to by the MAR
10. Put the data read into the MR
11. Write the MR contents back into memory at the MAR address (rewrite)

This cycle applies to every MIER instruction.

The program start address is entered using the Start Address Switches (STAS) on the control panel.

The MIER instruction set

Instruction	Action	Instruction code
Clear and add	AC:= MR	ADC   000 000
Clear and add the absolute value	AC:= MR	AVC   000 001
Add	AC:= AC + MR	ADD  000 010
Logical addition	AC:= logic OR(AC, MR)	ADL   000 011
Clear and subtract	AC:= – MR	SUC   000 100
Subtract	AC:= AC – MR	SUB    000 101
Multiply	AC:= MQ * MR	MLY   000 110
Multiply logical	AC:= logic AND(MQ,  MR)	MLL   000 111
Divide	MQ:= AC / MR	DIV    001 000
Transfer Unconditional	Jump to DAR address	TUN   001 001
Transfer and               Set Return Address	Store address+1 at DAR; next instruction is at DAR+1	TSR   001 010
Transfer to Return Address		TTR    001 011
Transfer if AC < 0	Jump to DAR if AC<0	TNE    001 100
Transfer if AC = 0	Jump to DAR if AC=0	TZE    001 101
Store AC	AC to MAR address	SAC    001 110
Load MQ	AC:= MQ	LMQ   001 111
Store MQ	MQ:= AC	SMQ  010 000
Load MOR	MOR:= AC	LMO  010 001
Store MOR	AC:= MOR	SMO  010 010
Shift AC + MQ bits left/right	Shift AC and MQ content; the least significant bit of AC becomes the sign bit of MQ	SHI   010 011
Load IOD internal (via DAR)	MR to IOD	LDI    010 100
Load IOD external (via IOA)	MR to IOD	LDE   010 101
Store IOD internal (via DAR)	IOD to MR	SDI    010 110
Store IOD external (via IOA)	IOD to MR	SDE   010 111
Load IOA	MR to IOA	LAD  011 000
Load IOD (address)	MAR to IOD	LAA  011 101
Input	IC to IOD/IOA	INP   011 010
Output	IOD/IOA to IOC	OUT  011 011
NOP (no operation)		NOP  011 100
Set Flag-flip-flop n	Flag-flop-flop n:= 1	SFF  011 101
Reset FLAG-Flip-flop	Flag flip-flop n:=0	RFF  011 110
Stop	Stop the MIER	STP  011 111
Address Modification (indirect addressing)	instructions above with MAR:= DAR + MOR	1xx xxx

Papertape

The 8-channel papertape is produced on an electric typewriter that is linked to the PROprogramma paper tape SAmensteller (PROSA). The PROSA electronics converts the typewriter code into a code that the MIER can understand. The word content is divided into groups of three bits each: 1, 2-4, 5-7, 8-10, 11-13, 14-16 and 17-19. Track 8 contains the parity bit (per character).
Both the papertape reader and the papertape puncher were developed at the laboratory because of the non-ASCII code used by the MIER.

When reading the papertape, the parity bit is used to monitor the correct reading. If an odd number of bits is encountered (parity error), the tape is stopped. The control track (track 7) of the papertape controls the storage in the memory of an instruction or data word and whether the papertape has been read to its end. A First Address Block (FOB) coding is first read to indicate the (start) location of the code in memory. That makes it possible to read and load more paper tapes (code parts) in succession.
A papertape can also contain data only. To read such a papertape, a built-in program in the MIER is used.

 

Built-in programs

The MIER has three built-in (hardware) programs. In addition, using the built-in flip-flops, Sense Switches and Interrupt control one can execute one’s programs:

1. Main program
   One can start a program in the following way:
   • With the switch in the position “CONTINUE”, the program continues from the point at which it was halted.
   • The “REPEAT” position repeats the operation that was stopped.
   • With the switch in the “PRESET” position, the program starts at the address selected with the 13 STAS switches.

   When the main program is running, the “COMPUTER” indicator lights up.

   One may stop the main program in the following ways:

   • Executing the “STOP” instruction.
   • Using the switch “SUC” (Stop unconditionally).
   • Using the switch “SC” (Stop conditionally).
   • Having the switch “READER” continuously switched ON.
   • Exceeding the own capacity: “OVERFLOW” signal. This signal is suppressed with the “OVERFLOW INHIBIT” switch. “OVERFLOW CLEAR” switch clears the interrupt again.
   • Using incorrect instructions with incorrect parity.
   • Using the switch “STEP”. The computer advances a single switch step (0.5 µsec) a time.
2. The papertape reader programme
   is activated when the “READER” switch is ON. Reading starts:
   • When reading a “SET Flip-Flop (011 101)” instruction during the execution of the main program.
   • After an action with the “READER” switch. This also stops the program.
   • With a stop “SUC” instruction. The program can then be continued.
   • Reading starts also when the “start switch on/off” is activated with the selector switch in the “WRITE” position.
   • Reading can also be started with the “cont” or “cont.count” switch positions.
3. Import and export programs
   • Manually enter the memory address (13 STAS switches) and data (19 DSR switches) on the control panel.
   • Set a memory address with the STAS switches, transfer it to the MR register and make it visible.
   • Put the DSR switch positions into a register./li>
4. Control of specific circuits, the flip-flops, Sense Switches, and the Interrupt Switch.
   • In a program, the values of the flip-flops and Sense Switch can be set using accumulator AC1. Predetermined actions can be performed from this accumulator.
   • By setting a flip-flop from, for example, a measuring system, a program is interrupted or if this flip-flop is set using a switch on the MIER control panel. A subroutine is then executed. Afterwards, the interrupted program will be continued.

Sources

1. J.J.A. Vogel Msc (1972), Handleiding voor gebruikers van de MIER [“MIER user’s manual”]
2. Bram Leenhouts en het FEL-TNO: Herinneringen 1949-1987,