LEOK: Logic Micro Processor (LMP) for the MLT
LEOK’s Logic Micro Processor (LMP)
In 1977 a microprocessor system was designed for the Mech Lua Trainer project (MLT). Although the system is designed for the said project, the system has a more general potential.
The instruction repertoire of the microprocessor system focuses on performing logical operations (Boolean logic) in parallel on different sets of binary variables. A maximum of 512 variables can be addressed in a data collection. In addition, the processor has some computational facilities.
The field of application for the “Logic Micro Processor” (LMP) lies mainly in the realisation or simulation of digital controls where response times of some milliseconds are allowed. It is also possible to generate monostable states by synchronising the program execution with an external clock signal.
The LMP is realised using two European standard-sized printed circuit boards (PCB) with printed wiring (“Euro-6” format). Optionally, a control and monitor panel can be connected. The program memory of the LMP consists of programmable read-only memories (PROMs and REPROMs).
A mnemonic assembly language is defined for the instruction repertoire. Program commands in this assembly language are translated into object code by a cross-assembler on the LEOK computer system. Via a PROM programmer coupled to the “host” computer system, the object code is written into the PROMs and checked.