Computer historie: het ETA10-P systeem

Het ETA10-P systeem

Bij TNO werd een ETA10-P (systeem #23) geïnstalleerd onder Unix. Control Data besloot echter de ontwikkelingen te stoppen.
Hieronder de technische gegevens van de lijn van systemen en enige foto’s van de installatie.

ETA systems logo
ETA systems logo

ETA 10 functional diagram

ETA functional diagram
ETA functional diagram

All models in the family of ETA10 supercomputers were based on the same architecture as shown in the functional diagram above.

  • The ETA10 had, depending on model and type, from one to eight central processing units (CPUs), depending on model selection.
  • Each CPU included both a scalar processor and a vector processor:
    • The scalar processor was characterised by independent, segmented, functional units, a 256-word high-speed register file, and a 64-word instruction stack.
    • The vector processor operated in parallel with the scalar processor and the input/ output channels.
    • The vector processor could link the result of one vector to the input of the next vector instruction, thereby performing two operations on the input stream vector data.
  • Each CPU had four million 64-bit words of central processor (CP) memory.
  • Shared memory provided a large storage area that can be accessed by all system processors, and is available in sizes from 8 million to 256 million 64-bit words, depending on model selection.
  • The communication buffer provided a very high-speed memory common to all processors that allows them to communicate and coordinate activities.
  • 1 to 18 input/output units connected the ETA10 to peripherals and networks,
  • The service unit, a ring of Apollo DN3000 workstations and DSP90 server modes, provided the operator and maintenance interface.
  • The ETA10 operated with a standard 64 bit word length, optional 32-bit mode essentially doubled the memory capacity and vector speed, 128-bit double precision mode was also available.
  • The ETA10 could be readily field upgraded to incorporate more memory or processing power.

ETA 10 models

    P     Q   E

ETA 10-E at FSU, Florida
ETA 10-E at FSU, Florida
Cycle time (ns) 24 19 10.5 7
#processors 1 or 2 1 or 2 1-4 2-8
CPU memory
32 32 32 32
Shared memory (MB) 64-512 64-512 256-1024 512-2048
Peak performance
750 947 3,429 10,289
Cooling air air liquid nitrogen
liquid nitrogen
Max.# I/O units 4 4 9 16

On April 17, 1989, Control Data took the decision to stop ETA (see ETA Saga), seven LN2 and 27 air-cooled systems were installed at sites. In the Netherlands three single and double processor air cooled ETA10 systems were installed at the University of Groningen (RUG), computing centre of the Energy Centre Netherlands (ENR) and TNO-FEL.

Inside of the ETA-10P (
Inside of the ETA-10P (“Piper #23”) at TNO. Memory at the top, CPU board in the middle
ETA10-P CPU board and control boards at bottom.
ETA10-P CPU board and control boards at bottom


I/O unit and disk cabinet at right.
I/O unit and disk cabinet at right