CDC 6000 series: Peripheral Processors
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A Peripheral Processor or PP was logically a processor on its own with its own PP instruction set and programs. The main task of PP programs was input and output and housekeeping.
Each PP had 4096 words of 12 bits memory (see photo). This PP memory was equivalent to one core memory block. The later 180/800-series systems had 8K words of 16 bit SECDED memory. The limited instruction set of a PP allowed internal processing, read/write to Central Memory, read/write to I/O channels, and exchanging the CPU. A PP had only one accumulator and there were direct cells (like in the PDP8) that allowed efficient and compact 12-bit instructions.
PPs were organised in groups of ten (in the 800-series systems in groups of 5) or barrels. As said before, each PP was perceived as a single, separate processor in the system. In reality, only one hardware processor serviced a complete barrel of PPs. Using shift-registers, PP instructions were processed in either one, two or 5 minor (memory read/write) cycles. For the CYBER 840 system that meant that each PP register moved through the barrel at a 20 MHz rate, causing each PP to run at four MHz.
Each PP barrel had a:
- R(elocate) register (22 bits; 800 series only) forms, in conjunction with the A-register the absolute address for a CM read/write in the virtual state. When bit 17 of A was set, the R-register was extended with six zero bits at the lower (right) end before the contents of the A-register was added. Otherwise, only the A-register was used (6000/170-state).
- A(ddress) and Accumulator register (18 bits).
- P(rogram counter) (12 bits; 16 bits in the 800-series), contained the PP program address. The exceptions were the 61, 63, 71 and 73 instructions where P contained the PP memory address of the transfer. A deadstart, the P of all PPs was set to zero.
- Q register (12 bits; 16 bits in the 800-series): operand register during (in)direct addressing, the data pointer during CM-read/write, channel number, shift count and so on.
- K register (7 bits): operations code.
- 5-stage CM word read pyramid (60 bits on the 6000/70-series or 64 bits on the 800-series)
- 5-stage CM word write pyramid (60 bits on the 6000/70-series or 64 bits on the 800-series)
At a deadstart, all PPs were forced to program address zero and loop for input available on their “own” channel, PP0 – channel 0, PP1 – channel 1, etc. The bytes from the deadstart panel – a panel with toggle switches – were send onto channel 0 and thus forced into PP0. PP0 processed that program which normally was programmed to look for the next program part on either a deadstart tape or (later) on a specific disk section. In that way, PP0 bootstrapped the core of the operating system. Next, PP0 or M(oni)T(o)R was responsible to output the Standard Library (STL) to each PP by writing it to the subsequent hardware channels.
Deadstarts could be initiated by using a hardware button between the two console “eyes” or under the single console screen in later systems. Another way was using the deadstart switch adjacent to the deadstart panel. After some time, system programmers and operators were very experienced in “toggling in” the deadstart program in the 16 or 20 rows with switches. It was always amasing that one could (warm)start from a deadstart tape (later a disk) using only seven to twelve PP instructions on the deadstart panel.
Sample deadstart panel program
01 1402 LDN 2 load 2
02 73ch OAM out, ch output 2 words from address 17B onwards on ch
04 754ch DCN ch disconnect channel ch
05 77ch FNC 120B, ch put function 120B on ch
07 74ch ACN ch activate ch
10 71ch IAM 7301B,ch read (A) words from ch to address 7301 and next addresses
12 0710 MJN hang jump to address 0
20 7112 7112
21 0000 hang