CDC’s 180-state architectuur
* Vooralsnog wordt geen vertaling van deze pagina in het Nederlands voorzien
Like the Data General Eclipse in Tracey Kidder’s The Soul of a New Machine, CDC’s Cyber 180 machines could run in one of two modes or states: 170 state, which was basically the same as the old CDC 6000 line, and the new 180 state, which is what NOS/VE used. There was quite a bit of difference between the two. The 170 state was more RISCy than almost any current so-called RISC processor, such as Alpha, MIPS, or PowerPC. The 180 state was full-blown CISC, with virtual memory.
Some basic ideas of the GE (later Honeywell) Multics operating system and its underlying hardware requirements (security rings, virtual space) were stretched even further in the design of the 180-series and the NOS/VE system on top of it. In the mid eighties there were discussions about the port of Multics to the CYBER 180 platform.
In 180 state, the CDC 800, 900 and 2000 series of systems were full 64-bit machines. Memory was 64-bit word and 8-bit byte addressable. Integers were 64 bits long, though 32-bit integers were used for addresses in instructions. Floating point numbers were 64 bits for single precision, and 128 bits for double precision. Memory was numbered by bytes. Words in memory had to be stored at addresses that were multiples of 8. Memory was protected by SECDED bits; a definite improvement over the 6000 series, which didn’t even have parity!
The 180 series had a real-memory address space of 31 bits. Unlike the 170 (CDC 6000) series, 180 mode featured virtual memory. Page sizes ranged from 2048 to 65536 bytes in increments of powers of two, with NOS/VE supporting 2048 to 16386-byte pages.
180 CPU registers included 16 64-bit X registers for data, and 16 48-bit A registers for addresses. Unlike 170 state, there was no relationship between identically-numbered A and X registers, and memory loads and stores could be done from any X register. The P register was 64 bits wide. Unlike 170 state, integers were twos-complement.
Instructions could be 16, 32, or (apparently) 64 bits long. Multiple instructions could be packed into a 64-bit word, and a 32-bit instruction could be broken between words. However, apparently 64-bit instructions could not be broken between words.
The CPU instruction set included instructions to:
- Perform integer arithmetic (add, subtract, multiply, divide)
- Perform floating-point arithmetic (add, subtract, multiply, divide)
- Move, edit, and translate character strings
- Perform packed and unpacked decimal arithmetic
- Load or store fields on 64-bit word, 8-bit byte, and bit boundaries
- Extract or insert bit strings of 1 through 64 bits
- Load or store multiple A and X registers
- Normalize floating-point numbers
- Perform logical operations
- Perform shift operations
- Perform conditional branch tests
- Perform exchange jump operations
- Perform call and return operations
The CDC Cyber 800 series models 990 and 995 and the 2000 series also supported vector processing instructions, which implemented:
- Integer vector arithmetic
- Integer vector compare
- Logical vector arithmetic
- Integer / floating point vector conversion
- Floating-point vector arithmetic
- Circular shift
- Merge, scatter, and gather operations with fixed stride
- Summation of a floating-point vector
(These tables were taken from page 26 of the CDC publication listed below.)
Here is a diagram of a 32-bit instruction to load X4 with the contents of the memory word at the address in A5:
|8 bits||4 bits||4 bits||16 bits|
|82 hex||5 (A reg)||4 (X reg)||0 (displacement)|
Here is a diagram of a 32-bit instruction to store XE (14th X register) into the memory word at the address in A6 plus 8*3. For word stores like this, the displacement field of the instruction is multiplied by 8 before being added to the contents of the A register to get the address:
|8 bits||4 bits||4 bits||16 bits|
|83 hex||6 (A reg)||E (X reg)||3 (displacement in words)|
Hardware debugging support
A programmer can instruct 180 mode to issue an interrupt whenever one or more of these conditions is met for a specified area in virtual memory:
- Data is read from the area.
- Data is written to the area.
- An instruction is fetched from the area.
- A branch is made to the area.
- A call is made to the area.
You can set a debug interrupt for any combination of these five conditions for up to 32 different areas in virtual memory.
(The above tables were taken from page 26 of the CDC publication listed below.)
180 state used a subroutine call mechanism that is fairly conventional by modern standards. A stack is used for the return address and for local variables. A stack frame contained certain “mandatory registers”; my source does not specify them but clearly the P register must have been one of them. The caller could specify that certain caller-designated A and X registers also be pushed onto the stack during a call.
Source for this information
Like most 180 state programmers, most programmers only vaguely aware of 180 state architecture. Assembly language was not a part of 180 state culture as it had been with the CDC 6000 series. Therefore, nearly all of the information presented here is from a 60-page CDC document titled CYBER 180 Computer Systems System Architecture. The copy is dated 3/84.
This document is one of a series of 12 documents giving overviews of various aspects of CDC’s new line of computers. Each had a cover featuring a large (over half of life-size) photograph of a person. It was amusing to note that none of the twelve supposed Cyber users depicted was a young white male.
(with special thanks to Mark Riordan, MSU who provided the basis for this page)